NDLI: Microelectronic Systems Education in the Global Economy Era

Content Provider	IEEE Xplore Digital Library
Author	Rucinski, A. Bouldin, D.
Copyright Year	2007
Description	Author affiliation: Univ. of New Hampshire, Durham (Rucinski, A.)
Abstract	Currently, fewer ASIC designers are needed as before and the creation of intellectual property (IP) blocks is being performed in developing countries like India. As a result of this shift in design practices, a microelectronic design methodology that: (1) de-emphasize our traditional ASIC design and fab courses, and (2) concentrates on system integration of IP blocks for programmable SoCs such as XILINX VirtexII-Pro becomes an attractive alternative to more traditional ASIC style experiences. Both the University of New Hampshire and the University of Tennessee are restructuring our own curricula to respond to these challenges. We do not plan to eliminate entirely our custom VLSI courses which deal with physical level issues such as signal integrity, design for testability and design for manufacturability. However, we recognize that the number of ASIC design starts is continuing to go down while the number of FPGA designs is increasing. At the same time, we realize that globalization of engineering design means that many of the IP blocks needed for applications will be designed overseas, not in the USA. On the bright side, we believe that US designers will still be needed but will focus more on customizing FPGA platforms to the needs of local customers. Thus, we need to emphasize our FPGA-based courses even more than in the past and concentrate on providing students with team projects that sharpen their skills in developing specifications, integrating IP blocks and filling in new ones where needed, and in verification using both simulation and FPGA-based prototype boards. Because of collaboration, learning management tools, non-technical and technical components become equally important. Both centralized and global educational models are presented and collaboration scenarios proposed for consideration and discussion.
Starting Page	83
Ending Page	83
File Size	107572
Page Count	1
File Format	PDF
ISBN	076952849X
DOI	10.1109/MSE.2007.64
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microelectronics Application specific integrated circuits Field programmable gate arrays Intellectual property Design methodology Very large scale integration Design for testability Signal design Manufacturing Globalization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Learning VLSI design using programmable logic arrays

Fast Robust Intellectual Property Protection for VLSI Physical Design

VLSI Designer's Interface

Field programmable gate array design for an application specific signal processing algorithms

Programmable DSP systems using FPGA

Distributed Curriculum In Microelectronic Systems

Automating the packaging selection of VLSI systems

University LSI Design Contest

University LSI Design Contest

Microelectronic Systems Education in the Global Economy Era

Similar Documents

Learning VLSI design using programmable logic arrays

Fast Robust Intellectual Property Protection for VLSI Physical Design

VLSI Designer's Interface

Field programmable gate array design for an application specific signal processing algorithms

Programmable DSP systems using FPGA

Distributed Curriculum In Microelectronic Systems

Automating the packaging selection of VLSI systems

University LSI Design Contest

University LSI Design Contest

Microelectronic Systems Education in the Global Economy Era