NDLI: STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches

Content Provider	IEEE Xplore Digital Library
Author	Dongyuan Zhan Hong Jiang Seth, S.C.
Copyright Year	2010
Abstract	Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key observations, based on our study of LLCs: 1) the capacity demand is highly non-uniform and dynamic at the set level, and 2) neither spatial nor temporal LLC management schemes, working separately as in prior work, can consistently and robustly deliver the best performance under different circumstances. Therefore, we propose a novel adaptive scheme, called STEM, which concurrently and dynamically manages both spatial and temporal dimensions of capacity demands at the set level. In the proposed scheme, a set-level monitor captures the temporal and spatial capacity demands of individual working sets and judiciously pairs off sets with complementary capacity demands so that the underutilized set in each pair can cooperatively cache the other’s victim blocks. The controller also decides on the best temporal sharing patterns for the coupled sets in the event of inter-set space sharing. Further, if the LLC controller cannot find a complementary set for a particular set, STEM can still decide on the best set-level replacement policy for it. Our extensive execution-driven simulation data shows that the proposed scheme performs robustly and consistently well under various conditions.
Starting Page	163
Ending Page	174
File Size	507374
Page Count	12
File Format	PDF
ISBN	9781424490714
ISSN	10724451
DOI	10.1109/MICRO.2010.31
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Measurement Monitoring Robustness Organizations System-on-a-chip Resource management Cooperative Caching Chip Multiprocessors Last Level Cache Management Set-Level Non-Uniformity of Capacity Demands
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches

Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching

Spatiotemporal capacity management for the last level caches of chip multiprocessors (2012).

Spatiotemporal Capacity Management for the Last Level Caches of Chip Multiprocessors

Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems

to Enhance CMP Cooperative Caching*

Locality & utility co-optimization for practical capacity management of shared last level caches

Cooperative Caching for Chip Multiprocessors

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STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches

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