NDLI: Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Content Provider	IEEE Xplore Digital Library
Author	Teodorescu, R. Nakano, J. Tiwari, A. Torrellas, J.
Copyright Year	2007
Description	Author affiliation: Univ. of Illinois at Urbana, Urbana (Teodorescu, R.; Nakano, J.; Tiwari, A.; Torrellas, J.)
Abstract	Parameter variation is detrimental to a processor's frequency and leakage power. One proposed technique to mitigate it is fine-grain body biasing (FGBB), where different parts of the processor chip are given a voltage bias that changes the speed and leakage properties of their transistors. This technique has been proposed for static application, with the bias voltages being programmed at manufacturing time for worst-case conditions. In this paper, we introduce dynamic FGBB (D-FGBB), which allows the continuous re-evaluation of the bias voltages to adapt to dynamic conditions. Our results show that D-FGBB is very versatile and effective. Specifically, with the processor working in normal mode at fixed frequency, D-FGBB reduces the leakage power of the chip by an average of 2%-A2.% compared to static FGBB. Alternatively, with the processor working in a high-performance mode, D-FGBB increases the processor frequency by an average of 7-9% compared to static FGBB - or 7-16% compared to no body biasing. Finally, we also show that D-FGBB can be synergistically combined with dynamic voltage and frequency scaling (DVFS), creating an effective means to manage power.
Starting Page	27
Ending Page	42
File Size	1537716
Page Count	16
File Format	PDF
ISBN	9780769530475
ISSN	10724451
DOI	10.1109/MICRO.2007.43
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Temperature Dynamic voltage scaling Manufacturing Delay Microarchitecture Energy management Process design Process control Fabrication
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

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