NDLI: Modulo scheduling with integrated register spilling for clustered VLIW architectures

Content Provider	IEEE Xplore Digital Library
Author	Zalamea, J. Llosa, J. Ayguade, E. Valero, M.
Copyright Year	2001
Description	Author affiliation: Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain (Zalamea, J.; Llosa, J.; Ayguade, E.; Valero, M.)
Abstract	Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers and functional units are grouped in clusters so that new instructions are needed to move data between them. New aggressive instruction scheduling techniques are required to minimize the negative effect of resource clustering and delays in moving data around. In this paper we present a novel software pipelining technique that performs instruction scheduling with reduced register requirements, register allocation, register spilling and inter-cluster communication in a single step. The algorithm uses limited backtracking to reconsider previously taken decisions. This backtracking provides the algorithm with additional possibilities for obtaining high throughput schedules with low spill code requirements for clustered architectures. We show that the proposed approach outperforms previously proposed techniques and that it is very scalable independently of the number of clusters, the number of communication buses and communication latency. The paper also includes an exploration of some parameters in the design of future clustered VLIW cores.
Sponsorship	IEEE TC-MARCH ACM SIGMICRO
Starting Page	160
Ending Page	169
File Size	1123789
Page Count	10
File Format	PDF
ISBN	0796513697
ISSN	10724451
DOI	10.1109/MICRO.2001.991115
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-12-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Registers Processor scheduling Pipeline processing Energy consumption Throughput Computer architecture Scheduling algorithm Logic Dynamic scheduling
Content Type	Text
Resource Type	Article

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