NDLI: Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

Content Provider	IEEE Xplore Digital Library
Author	Davidson, J.W. Jinturkar, S.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA (Davidson, J.W.; Jinturkar, S.)
Abstract	Exploitation of instruction-level parallelism is an effective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism. This paper describes and evaluates a software technique, dynamic memory disambiguation, that permits loops containing loads and stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism. The results of our evaluation show that when dynamic memory disambiguation is applied in conjunction with loop unrolling, register renaming, and static memory disambiguation, the ILP of memory-intensive benchmarks can be increased by as much as 300 percent over loops where dynamic memory disambiguation is not performed. Our measurements also indicate that for the programs that benefit the most from these optimizations, the register usage does not exceed the number of registers on mast high-performance processors.
Starting Page	125
Ending Page	132
File Size	836282
Page Count	8
File Format	PDF
ISBN	0818673494
ISSN	10724451
DOI	10.1109/MICRO.1995.476820
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Registers Hardware Computer science VLIW Processor scheduling Dynamic scheduling Performance evaluation Pipelines Program processors
Content Type	Text
Resource Type	Article

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