NDLI: BIST for ring-address SRAM-type FIFOs

Content Provider	IEEE Xplore Digital Library
Author	van de Goor, A.J. Schanstra, I. Zorian, Y.
Copyright Year	1994
Description	Author affiliation: Delft Univ. of Technol., Netherlands (van de Goor, A.J.; Schanstra, I.)
Abstract	Testing FIFOs involves testing the embedded memory cell array, the addressing mechanisms, and the FIFO functionality logic (such as Empty and Full flags); each with their specific fault models. A test algorithm for the popular ring-address SRAM-type FIFOs has been published [Go94]; it consists of 36 steps and has a test length of 2n/sup 2/+10n+12+2/spl middot/Del (where n is the number of cells in the FIFO, and Del a delay time), while not all coupling faults are detectable due to the addressing restrictions of the FIFO. This paper presents a new test algorithm based on BIST which consists of 25 steps, reduces the test length to 21n+13+2/spl middot/Del, and allows for full fault coverage. It has been implemented as part of a macro-cell generator for FIFOs at AT&T Microelectronics. The paper describes the test algorithm, the BIST hardware, and the chip area overhead.
Starting Page	112
Ending Page	118
File Size	637275
Page Count	7
File Format	PDF
ISBN	081866245X
DOI	10.1109/MTDT.1994.397188
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit faults Circuit testing Logic testing Logic arrays Hardware Decoding Shift registers Added delay Delay effects
Content Type	Text
Resource Type	Article

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