NDLI: Power-gating current test for static RAM in nanotechnologies

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Wei Chao Hsin-Ling Chen Chih-Jong Chen Tsung-Chu Huang
Copyright Year	2007
Description	Author affiliation: Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua (Yuan-Wei Chao; Hsin-Ling Chen; Chih-Jong Chen; Tsung-Chu Huang)
Abstract	Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.
Starting Page	42
Ending Page	45
File Size	377334
Page Count	4
File Format	PDF
ISBN	9781424416561
ISSN	10874852
DOI	10.1109/MTDT.2007.4547614
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-03
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing CMOS technology Random access memory Logic testing Read-write memory Electronic equipment testing Decoding Switches Acceleration Energy management
Content Type	Text
Resource Type	Article

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