NDLI: A parallel built-in diagnostic scheme for multiple embedded memories

Content Provider	IEEE Xplore Digital Library
Author	Li-Ming Denq Rei-Fu Huang Cheng-Wen Wu Yeong-Jar Chang Wen-Ching Wu
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., National Tsing Hua Univ., Hsinchu, Taiwan (Li-Ming Denq; Rei-Fu Huang; Cheng-Wen Wu)
Abstract	Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing memory optimization and reconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required.
Starting Page	65
Ending Page	69
File Size	244729
Page Count	5
File Format	PDF
ISBN	0769521932
ISSN	10874852
DOI	10.1109/MTDT.2004.1327986
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Built-in self-test System testing System-on-a-chip Sequential diagnosis Memory architecture Constraint optimization Geometry Test pattern generators Production
Content Type	Text
Resource Type	Article

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