NDLI: Rambist builder: a methodology for automatic built-in self-test design of embedded rams

Content Provider	IEEE Xplore Digital Library
Author	Rajsuman, R.
Copyright Year	1996
Description	Author affiliation: LSI Logic (Rajsuman, R.)
Abstract	In this paper, we report a built-in self-test methodology for embedded RAMs. A CAD tool has been developed to synthesize the BIST circuitry for the compiled RAMs. The blocks such as address generator, pattern generator, multiplexers, state machine, control logic and comparator are automatically synthesized with this tool. The BIST logic is personalized to the RAM configuration and its physical bit map. This provides coverage of all stuck-at, state transition and coupling faults. In multi-port RAMs port-coupling faults are also detected. RAM addresses are generated by the address generator based upon the March algorithm. A set of multiplexers selects the path to the address, data and control lines, either from the RAM (during normal operation), or from the pattern generator (during test mode). The state machine and control logic provide signals for read, write, port selection and start/end. A comparator evaluates the data written during the write cycle against the RAM's output data to generate a pass/fail flag.
Starting Page	50
Ending Page	56
File Size	572922
Page Count	7
File Format	PDF
ISBN	0818674660
ISSN	10874852
DOI	10.1109/MTDT.1996.782492
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-08-13
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit faults Random access memory Circuit testing Automatic testing Application specific integrated circuits Read-write memory Circuit synthesis Logic testing Design automation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Testing embedded RAMs in ASIC chips

BIST for embedded static RAMs with coverage calculation

Testing embedded single and multi-port RAMs using BIST and boundary scan

Designing built-in self-test circuits for embedded memories test

Embedded RAM testing

Built-in random testing for dual-port RAMs

A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs

Built-in self-test for multi-port RAMs

Testing Embedded Memories: Is Bist The Ultimate Solution? An Asic Designer's Point Of View

Rambist builder: a methodology for automatic built-in self-test design of embedded rams

Similar Documents

Testing embedded RAMs in ASIC chips

BIST for embedded static RAMs with coverage calculation

Testing embedded single and multi-port RAMs using BIST and boundary scan

Designing built-in self-test circuits for embedded memories test

Embedded RAM testing

Built-in random testing for dual-port RAMs

A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs

Built-in self-test for multi-port RAMs

Testing Embedded Memories: Is Bist The Ultimate Solution? An Asic Designer's Point Of View

Rambist builder: a methodology for automatic built-in self-test design of embedded rams