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  1. IEEE International Workshop on Memory Technology, Design and Testing.
  2. Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
  3. Unbalanced cache systems
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2009 IEEE International Workshop on Memory Technology, Design, and Testing
2007 IEEE International Workshop on Memory Technology, Design and Testing
2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)
2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)
Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.
Records of the 2003 International Workshop on Memory Technology, Design and Testing
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing
Records of the IEEE International Workshop on Memory Technology, Design and Testing
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
Computing in memory architectures for digital image processing
Unbalanced cache systems
The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval
Failure mechanisms detected in memory chips during routine construction analysis
Interconnect diagnosis of bus-connected multi-RAM systems
Determining redundancy requirements for memory arrays with critical area analysis
Design validation of .18 /spl mu/m 1 GHz cache and register arrays
Tutorial: characterizing SDRAMs
Built in self test for ring addressed FIFOs with transparent latches
A fast test to generate flash memory threshold voltage distribution map
Modeling and testing transistor faults in content-addressable memories
Designing a memory module tester
A comparative simulation study of four multilevel DRAMs
The potential of carbon-based memory systems
Low-power SRAM circuit design
A tribute to graphics DRAMs
Author index
Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)
Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159)
IEEE International Workshop on Memory Technology, Design and Testing,
Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Proceedings of IEEE International Workshop on Memory Technology, Design, and Test
Records of the 1993 IEEE International Workshop on Memory Testing

Unbalanced cache systems

Content Provider IEEE Xplore Digital Library
Author Rhodes, D.L. Wolf, W.
Copyright Year 1999
Description Author affiliation: Res., Dev. & Eng. Center, US Army CECOM, Fort Monmouth, NJ, USA (Rhodes, D.L.)
Abstract The new concept of an unbalanced, hierarchically-divided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different memory references (e.g. as possibly unevenly divided within an address-space) to be subject to various levels of caching as well as varied amounts of cache at each level. Under the assumption that the total cache size at a particular level is fixed, it is easily shown that at least one divided cache structure exists for which the miss-rate is the same as a single unified cache. By using alternate implementations, however, the method may provide a significant decrease in miss-rates as is shown via simulations. Specifically, SPEC95 benchmarks are used to demonstrate that the technique is effective for general usage but it may be even more useful for embedded systems where memory access patterns can be more fully controlled (i.e. via the compiler). In addition to improved miss-rates, another advantage is that the hit-time for multiple smaller caches may be smaller than for a single larger cache. Disadvantageous, but readily surmountable, electrical aspects are also discussed.
Starting Page 16
Ending Page 23
File Size 157371
Page Count 8
File Format PDF
ISBN 0769502598
ISSN 10874852
DOI 10.1109/MTDT.1999.782679
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 1999-08-09
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Delay Electronic switching systems Electrical capacitance tomography Reactive power Very large scale integration Computer aided instruction Microprocessors Digital signal processors Digital signal processing VLIW
Content Type Text
Resource Type Article
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