NDLI: Challenges in memory-logic integration

Content Provider	IEEE Xplore Digital Library
Author	Prince, B.
Copyright Year	1995
Description	Author affiliation: Meomory Strategies Int., Sugarland, TX, USA (Prince, B.)
Abstract	This overview paper discusses sore of the system opportunities and the manufacturing costs of integrating large amounts of logic and memory on a single chip.
Starting Page	2
Ending Page	7
File Size	639337
Page Count	6
File Format	PDF
ISBN	0818671025
DOI	10.1109/MTDT.1995.518074
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-08-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Random access memory Silicon Graphics Drives Pulp manufacturing Paper technology Seminars Logic design Reliability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Challenges in memory-logic integration