NDLI: A new fabric of reconfigurable FFT processor for high-speed and low-cost system

Content Provider	IEEE Xplore Digital Library
Author	Huan Liu Wei Pan Shui-Sheng Lin
Copyright Year	2008
Description	Author affiliation: Sch. of Commun. & Inf. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu (Huan Liu; Wei Pan; Shui-Sheng Lin)
Abstract	A high-speed reconfigurable FFT architecture based on FPGA is proposed in this paper. The system can be configured as 32, 64,128, 256, 512 and 1024-point FFT using simplified method to control. It has been synthesized in Xilinx Virtex2p FPGA and post-simulated. Compared with Xilinx FFT IP Core with the same function, this FFT fabric proposed has saved almost 8%~9% (equivalent gates) in resources consumption while increased nearly 6%~25% in clock frequency and decreased 56~116 cycles of delays from first input data to the first result data, indicating high computing efficiency. On the other hand, power consumption is also slightly fewer than the IP Corepsilas. The fabric we presented in this paper is suitable for use in digital signal process with high-speed and low-cost.
Starting Page	3525
Ending Page	3529
File Size	407148
Page Count	5
File Format	PDF
ISBN	9781424420957
DOI	10.1109/ICMLC.2008.4621014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital multimedia broadcasting Field programmable gate arrays IP networks Fabrics Computer architecture Clocks Generators FPGA Reconfigurable FFT
Content Type	Text
Resource Type	Article

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