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Content Provider | IEEE Xplore Digital Library |
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Author | Jamil-Ur-Rehman Ye Zhang |
Copyright Year | 2005 |
Description | Author affiliation: Dept. of Electron. & Commun. Eng., Harbin Inst. of Technol., China (Jamil-Ur-Rehman; Ye Zhang) |
Abstract | H.264 adapts rate distortion optimization (RDO) technique to get high coding rate and visual quality. Because RDO is too much exhaustive, several attempts have been made to explore fast algorithms. In all algorithms computational speed increased with a performance degradation. In the previous attempts only two variables were considered i.e. computational speed (CS) and performance (P). In this paper we also considered a third variable production cost (PC). In microelectronics devices, FPGA or ASIC, parallel processing enhances computation speed with the increase in production cost. In some cases when no compromise on performance, parallel processing is an effective tool to overcome computational complexity. |
Sponsorship | IEEE Syst., Man and Cybernetics Tech. Comm. on Cybernetics, Hong Kong Polytechnic Univ. Hebei Univ. South China Univ. Chongqing Univ. Sun Yat-sen Univ. Harbin Inst. of Technol. and Int. Univ. in Germany |
Starting Page | 5094 |
Ending Page | 5098 |
File Size | 319723 |
Page Count | 5 |
File Format | |
ISBN | 0780390911 |
DOI | 10.1109/ICMLC.2005.1527841 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2005-08-18 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Parallel processing Production Costs Rate-distortion Degradation Microelectronics Field programmable gate arrays Application specific integrated circuits Concurrent computing Computational complexity H. 264 Intra prediction |
Content Type | Text |
Resource Type | Article |
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