NDLI: Low power considerations in the design of pipelined FIR filters

Content Provider	IEEE Xplore Digital Library
Author	Nagendra, C. Owens, R.M. Irwin, M.J.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA (Nagendra, C.; Owens, R.M.; Irwin, M.J.)
Abstract	This paper discusses some design considerations in building deeply pipelined FIR filters using CMOS technology. Filters are good candidates for studying various design trade-offs. They have a regular structure where the multiply-accumulate cells (MACs) have unit fan-out. Hence, the output capacitance and consequently, power and delay, are dominated by the interconnect and clocking scheme which scale with circuit size.
Starting Page	32
Ending Page	33
File Size	254696
Page Count	2
File Format	PDF
ISBN	0780330366
DOI	10.1109/LPE.1995.482452
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Clocks Pipeline processing Equations Arthritis Circuits Encoding Computer science Design engineering Digital signal processing
Content Type	Text
Resource Type	Article

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Low power considerations in the design of pipelined FIR filters