NDLI: Impact of Technology Scaling on Energy Aware Execution Cache-Based Microarchitectures

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Why Hot Chips are No Longer "Cool"

Leakage Power Reduction by Dual-Vth Designs Under Probabilistic Analysis of Vth Variation

Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS

Technology Exploration for Adaptive Power and Frequency Scaling in 90nm CMOS

Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode

Improved Clock-Gating through Transparent Pipelining

Microarchitectural Techniques for Power Gating of Execution Units

SEPAS: A Highly Accurate Energy-Efficient Branch Predictor

Understanding the Energy Efficiency of Simultaneous Multithreading

Impact of Technology Scaling on Energy Aware Execution Cache-Based Microarchitectures

Single-VDD and Single-VT Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches

Design and Implementation of Correlating Caches

Dynamic Power Management for Streaming Data

Delayed Line Bus Scheme: A Low-Power Bus Scheme for Coupled On-Chip Buses

Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages

Creating a Power-Aware Structured ASIC

Dynamic Voltage Scaling for Systemwide Energy Minimization in Real-Time Embedded Systems

ESACW: An Adaptive Algorithm For Transmission Power Reduction In Wireless Networks

Any-time Probabilistic Switching Model using Bayesian Networks

Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits

Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation

Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device

4T-Decay Sensors: A New Class of Small, Fast, Robust, and Low-Power, Temperature/Leakage Sensors

HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction

Location Cache: A Low-Power L2 Cache System

A Way-Halting Cache for Low-Energy High-Performance Systems

Soft Error and Energy Consumption Interactions: A Data Cache Perspective

Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion

Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing

Active Mode Leakage Reduction Using Fine-Grained Forward Body Biasing Strategy

A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations

Maximizing Efficiency of Solar-Powered Systems by Load Matching

Power Utility Maximization for Multiple-Supply Systems by a Load-Matching Switch

Dynamic Voltage and Frequency Scaling based on Workload Decomposition

Architecting Voltage Islands in Core-Based System-on-a-Chip Designs

Balanced Energy Optimization

Battery Life Challenges on Future Mobile Notebook Platforms

Approaches to Run-Time and Standby Mode Leakage Reduction in Global Buses

Spatial Encoding Circuit Techniques for Peak Power Reduction of On-Chip High-Performance Buses

A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems

Limited Intra-Word Transition Codes: An Energy-Efficient Bus Encoding for LCD Display Interfaces

Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors

Power-Optimal Pipelining in Deep Submicron Technology

Application-Level Prediction of Battery Dissipation

Minimizing Power Consumption and Complexity in a Programmable Transmit Filter Bank for OFDM

On Optimality of Adiabatic Switching in MOS Energy-Recovery Circuit

Constant-Load Energy Recovery Memory for Efficient High-Speed Operation

A Comparative Study of MOS VCOs for Low Voltage High Performance Operation

A CPL-Based Dual Supply 32-bit ALU for Sub 180nm CMOS Technologies

A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

Integrated Adaptive DC/DC Conversion with Adaptive Pulse-Train Technique for Low-Ripple Fast-Response Regulation

Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation

2.45 GHz Power and Data Transmission for a Low-Power Autonomous Sensors Platform

Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design

Architectures for Low Power Ultra-Wideband Radio Receivers in the 3.1-5GHz Band for Data Rates < 10Mbps

Low-Power Asynchronous Viterbi Decoder for Wireless Applications

A CMOS Even Harmonic Mixer with Current Reuse For Low Power Applications

A Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP

The Design of a Low Power Asynchronous Multiplier

Low-Power Fixed-Width Array Multipliers

Low-Power Carry-Select Adder Using Adaptive Supply Voltage Based on Input Vector Patterns

Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming

Understanding Nanoscale Conductors

Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization

Mitigating Inductive Noise in SMT Processors

Energy-Aware Demand Paging on NAND Flash-based Embedded Storages

Application Adaptive Energy Efficient Clustered Architectures

The Impact of Variability on Power

Reducing Radio Energy Consumption of Key Management Protocols for Wireless Sensor Networks

Evaluating and Optimizing Power Consumption of Anti-Collision Protocols for Applications in RFID Systems

Experience With A Low Power Wireless Mobile Computing Platform

FSM-Based Power Modeling of Wireless Protocols: the Case of Bluetooth

Efficient Adaptive Voltage Scaling System Through On-Chip Critical Path Emulation

An Efficient Voltage Scaling Algorithm for Complex SoCs with Few Number of Voltage Modes

Memory-Aware Energy-Optimal Frequency Assignment for Dynamic Supply Voltage Scaling

Preemption-Aware Dynamic Voltage Scaling in Hard Real-Time Systems

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

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ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

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Impact of Technology Scaling on Energy Aware Execution Cache-Based Microarchitectures

Content Provider	IEEE Xplore Digital Library
Author	Talpes, E. Marculescu, D.
Copyright Year	2004
Description	Author affiliation: Carnegie Mellon University, Pittsburgh, PA (Talpes, E.)
Abstract	Reducing total power consumption in high performance microprocessors can be achieved by limiting the amount of logic involved in decoding, scheduling and executing each instruction. One of the solutions to this problem involves the use of a microarchitecture based on an Execution Cache (EC) whose role is to cache already done work for later reuse. In this paper, we explore the design space for such a microarchitecture, looking at how the cache size, associativity and replacement algorithm affect the overall performance and power efficiency. We also look at the scalability of this solution across next process generations, evaluating the energy efficiency of such caching mechanisms in the presence of increasing leakage power. Over a spectrum of SPEC2000 benchmarks, an average of 35% energy reduction is achieved for technologies ranging from 130nm to 90nm and 65nm, at the expense of a negligible performance hit.
Starting Page	50
Ending Page	53
File Size	154847
Page Count	4
File Format	PDF
ISBN	1581139292
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-11
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Microarchitecture Space exploration Energy consumption Microprocessors Logic Decoding Processor scheduling Algorithm design and analysis Scalability Power generation Measurement Performance Design
Content Type	Text
Resource Type	Article

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