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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Valluri, M. John, L. Hanson, H. |
| Copyright Year | 2003 |
| Description | Author affiliation: Comput. Archit. & Technol. Lab., The Univ. of Texas at Austin, TX, USA (Valluri, M.; John, L.; Hanson, H.) |
| Abstract | This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors with out-of-order issue logic. In this Hybrid-Scheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time completely bypass the dynamic scheduling logic and execute in a low power static mode. Simulation studies using the Wattch framework on several media-arid scientific benchmarks demonstrate large improvements in overall energy consumption of 43% in kernels and 25% in full applications with only a 2.8% performance degradation on average. |
| Sponsorship | ACM SIGDA IEEE Circuits & Syst. Soc. IEEE Solid-State Circuits Soc. IEEE Electron Devices Soc |
| Starting Page | 414 |
| Ending Page | 419 |
| File Size | 739173 |
| Page Count | 6 |
| File Format | |
| ISBN | 158113682X |
| DOI | 10.1109/LPE.2003.1231940 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-08-27 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Processor scheduling Dynamic scheduling Hardware Logic Laboratories Computer architecture Out of order Energy consumption Parallel processing VLIW |
| Content Type | Text |
| Resource Type | Article |
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