NDLI: LVDCSL: low voltage differential current switch logic, a robust low power DCSL family

Content Provider	IEEE Xplore Digital Library
Author	Somasekhar, D. Roy, K.
Copyright Year	1997
Description	Author affiliation: Purdue Univ., West Lafayette, IN, USA (Somasekhar, D.)
Abstract	In this paper we present a robust Differential Current Switch Logic gate suitable for low V/sub DD/, low power operation. Differential Current Switch Logic gates achieve high performance and low power by restricting internal node voltage swings. Traditional DCSL is, however, highly sensitive to load imbalance because of the presence of a cross coupled inverter pair at the output. In this paper we describe LVDCSL, a low voltage DCSL family which preserves the essential features of DCSL namely, high speed, low power, restricted internal voltage swings and a latching input stage. However, it is much more robust to mismatched output loads, and is capable of working at far lower voltages. In addition spikes in output transitions are greatly reduced simplifying interface to conventional CMOS circuits. Our results show that LVDCSL is capable of working at under 2 volts in a 0.35 /spl mu/m CMOS process while being faster than comparable Domino gates. At the same time total power consumption is reduced. LVDCSL achieves 40% delay improvement and 22% power reduction in comparison with Domino gates.
Starting Page	18
Ending Page	23
File Size	554929
Page Count	6
File Format	PDF
ISBN	0897919033
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-08-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Switches Low voltage Robustness Logic gates Logic circuits CMOS logic circuits Energy consumption Permission CMOS process Switching circuits
Content Type	Text
Resource Type	Article

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