NDLI: On the latency bound of pre-order deficit round robin

Content Provider	IEEE Xplore Digital Library
Author	Kanhere, S.S. Sethu, H.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA (Kanhere, S.S.; Sethu, H.)
Abstract	In the emerging high-speed packet-switched networks, packet scheduling algorithms used in the switches and routers will play a critical role in satisfying the quality of service (QoS) requirements of various applications. The latency bound of a scheduling discipline is an important QoS parameter, especially for real-time playback applications. Frame-based schedulers such as deficit round robin (DRR), though extremely efficient with an O(1) dequeuing complexity, lead to high latencies due to bursty transmissions of each flow's traffic. In a previous work by, Tsao and Lin (see Computer Networks, vol.35, no.2-3, p.287-305, 2001), the authors propose pre-order deficit round robin, a novel scheme that overcomes this limitation of DRR while still achieving a low work complexity. In pre-order DRR, a priority queue module is appended to the original DRR scheduler which re-orders the packet transmission sequence in DRR to distribute the output more evenly among flows and thus reduce burstiness and improve the latency. We employ a novel approach to analytically derive the latency bound of pre-order DRR and show that our bound is a tight one. Our latency bound is significantly lower than the bound derived by Tsao and Lin, demonstrating that pre-order DRR has even better performance characteristics than previously argued by its own authors.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Commun
Starting Page	508
Ending Page	517
File Size	894337
Page Count	10
File Format	PDF
ISBN	0769515916
ISSN	07421303
DOI	10.1109/LCN.2002.1181824
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Round robin Quality of service Processor scheduling Scheduling algorithm Packet switching Switches Application software Telecommunication traffic Traffic control
Content Type	Text
Resource Type	Article

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