NDLI: Evolution of dopants and defects in silicon under various annealing sequences

Content Provider	IEEE Xplore Digital Library
Author	Mayur, A.J. Li, J.P. Adams, B. Moffatt, S. Ng, B. Moffitt, T. Howells, S. Hunter, A.
Copyright Year	2011
Description	Author affiliation: Applied Materials, Inc. 974 E Arques Avenue, Sunnyvale, CA 94085, USA (Mayur, A.J.; Li, J.P.; Adams, B.; Moffatt, S.; Ng, B.; Moffitt, T.; Howells, S.; Hunter, A.)
Abstract	Several decades of research into understanding the mechanisms responsible for diffusion and activation of group-III acceptor and group-V donor impurities in silicon has been driven by the technological need for creating electrical junctions in the S/D and extensions of transistors in semiconductor integrated circuits. It is now conclusively known that anomalous diffusion of implanted impurities during annealing results from their interaction with the non-conservative evolution of excess point-defect damage created by the original implantation, and the effect annealing ambients, co-impurities, interfaces and surfaces have on that evolution [1–8]. Early experiments shown in Ref. [2] conclusively proved this by etching away the surface region containing implant damage before annealing, and demonstrating that the anomalous behavior disappeared. Starting from the as-implanted damage, the nucleation, growth and dissolution of a sequence of larger defects at the expense of smaller ones during the anneal, sets the point defect flux and super-saturation levels (the ratio of point defect concentration to its temperature equilibrium value), which then determine the magnitude and durations of the various phases of anomalous diffusion [9].
Starting Page	122
Ending Page	127
File Size	1860891
Page Count	6
File Format	PDF
ISBN	9781612841311
e-ISBN	9781612841342
DOI	10.1109/IWJT.2011.5970015
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Annealing Boron Implants Silicon Heating Junctions Temperature
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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