NDLI: Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer

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Program-At-A-Glance

Materials and processes for high signal propagation performance and reliable 32 nm node BEOL

Highly-oriented PVD Ruthenium Liner for Low-resistance Direct-plated Cu Interconnects

Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric

The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

Chip-Package-Interaction Modeling of Ultra Low-k/Copper Back End of Line

A comparative study of thermal and plasma enhanced ALD Ta-N-C films on SiO2, SiCOH and Cu substrates

Integration and Interconnect Reliability of Warm A1 Process with CVD-A1 seed layer deposited using a novel precursor of TMAAB (trimethylarninealane borane)

The Development of an Innovative Process of Large Grained and Low Resistivity Cu Wires for less than hp 45nm ULSI

Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines

Cu / Barrier Metal Stack Film Characterization for Reliability Estimation

Reliability of Cu Interconnects with Ta Implant

Development of an Eco-friendly Copper Interconnect Cleaning Process

Design for Manufacturability in Backend Reliability and Packaging of Nanoscale Technologies

Electromigration Failure Mechanism and Lifetime Expectation for Bi-Modal Distribution in Cu/Low-k Interconnect

Air-gap transmission lines for multiprocessor interconnects on FR-4 and BT substrates

Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer

The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors

Advanced Cu/Low-k BEOL Integration, Reliability, and Extendibility

Multi-Level Cu Interconnects Integration and Characterization with Air Gap as Ultra-Low K Material Formed using a Hybrid Sacrificial Oxide / Polymer Stack

Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on Thermal Degradable Polymer and a SiOC CVD Hard Mask

A Highly Reliable Cu Interconnect Technology for Memory Device

Integration of High Performance and Low Cost Cu/Ultra Low-k SiOC(k=2.0) Interconnects with Self-formed Barrier Technology for 32nm-node and Beyond

Full Copper Electrochemical Mechanical Planarization (Ecmp) as a Technology Enabler for the 45 and 32nm Nodes

Toward a real system integration; A direction of IC technology

CMOS Integration of Capacitive, Optical, and Electrical Interconnects

Three dimensional chip stacking using a wafer-to-wafer integration

Technology and Design Cooperation: High-K MIM Capacitors for Microprocessor, IO, and Clocking

Impact of Cu microstructure on electromigration reliability

A Study of Adhesion and Improvement of Adhesion Energy Using Hybrid Low-k (porous-PAr/ porous-SiOC(k=2.3/2.3)) Structures with Multi-layered Cu Interconnects for 45-nm Node Devices

Chemical and Plasma Oxidation Behaviors of NiSi and NiPtSi Salicide Films in 65nm Node CMOS Process

An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond

Optimizing ALD WN Process for 65nm Node CMOS Contact Application

Mechanism and Application of Negative Charging Mode of Electron Beam Inspection for PMOS Leakage Detection

Assessing the Effect of Die Sealing in Cu/Low-k Structures

Extremely Low Keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC

Capacitance reduction effect using capping-layer removal process for porous low-k (k=2.5)/Cu system toward 45nm technology node

Mechanistic Study of Plasma Damage and CH4 Recovery of Low k Dielectric Surface

BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

Experimental Determination of the Toughness of Crack Stop Structures

Scaling of a Low Capacitance Highly Selective Self Aligned Contact Process

A Comparison of Voltage Ramp and Time Dependent Dielectric Breakdown Tests for Evaluation of 45nm Low-k SiCOH Reliability

The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks

Balancing Resistance and Capacitance of Signal Interconnects for Power Saving

Stress and Slurry Chemistry Effects on CMP Damage of Ultra-Low-k Dielectrics

Performance predictions of prospective air gap architectures for the 22 nm node

The Delay, Energy, and Bandwidth Comparisons between Copper, Carbon Nanotube, and Optical Interconnects for Local and Global Wiring Application

Line Edge Roughness of Metal Lines and Time-Dependent Dielectric Breakdown Characteristics of Low-k Interconnect Dielectrics

Impact of TaN/Ta copper barrier on full PEALD TiN/Ta2O5/TiN 3D damascene MIM capacitor performance

Study on Effect of Via Contour Distortion on Via Micro-void Formation in 45nm-node Process

The critical role of the metal / porous low-k interface in post direct CMP defectivity generation and resulting ULK surface and bulk hydrophilisation

Moving Away from Silicon: The Role of Interconnect in New Memory Technologies

Effect of the Hydrophilic-Lipophilic Balance (HLB) of Surfactants Included in the Post-CMP Cleaning Chemicals on Porous SiOC Direct CMP

Robust integration of an ULK SiOCH dielectric (k=2.3) for high performance 32nm node BEOL

Strategies of RC Delay Reduction in 45 nm BEOL Technology

45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications

Tera-scale Computing - the Role of interconnects in Volume Compute platforms

Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems

A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

Densification of Carbon Nanotube Bundles for Interconnect Application

Electrical Properties of Carbon Nanotube Via Interconnects Fabricated by Novel Damascene Process

Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs

Challenges for 3D IC integration: bonding quality and thermal management

Progress of 3D Integration Technologies and 3D Interconnects

2006 International Interconnect Technology Conference

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)

Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer

Content Provider	IEEE Xplore Digital Library
Author	Yi-Wei Chen Yu-Lan Chang Yi-Cheng Chen Shieh, K. Climbing Huang Tzou, S.F.
Copyright Year	2007
Description	Author affiliation: United Microelectron. Corp., Tainan (Yi-Wei Chen; Yu-Lan Chang; Yi-Cheng Chen; Shieh, K.; Climbing Huang; Tzou, S.F.)
Abstract	Ni(Pt) alloy has been implemented in the SiGe silicidation process for 65nm node CMOS device fabrication. A thin Si cap layer was introduced into the in-situ doped $Si_{1-x}Ge_{x}B$ film stack to further enhance the thermal stability of the silicide film. The Ni(Pt) germanosilicide temperature transition curves have been studied, N-/P-FET mismatch issues have been resolved, and a robust integration flow has been developed for the 65 nm node CMOS device fabrication.
Starting Page	37
Ending Page	39
File Size	223376
Page Count	3
File Format	PDF
ISBN	142441069X
DOI	10.1109/IITC.2007.382345
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Semiconductor films Silicon germanium Germanium silicon alloys Silicidation CMOS process Thermal stability Silicides Temperature Robustness
Content Type	Text
Resource Type	Article

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