NDLI: Interconnect material and CMP process change effects on local interconnect planarity

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Interconnect material and CMP process change effects on local interconnect planarity

Content Provider	IEEE Xplore Digital Library
Author	Mendonca, J. Dang, C. Pettinato, C. Cope, J. Garcia, H. Saravia, J. Farkas, J. Watts, D. Klein, J.
Copyright Year	1998
Description	Author affiliation: Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA (Mendonca, J.)
Abstract	With finer geometries and multiple metal levels, CMP planarity demands have increased at the lower device levels. Interconnect material changes (metals such as W, Ti, TiN and dielectrics such as BP-TEOS, HDP, and F-HDP) and CMP process changes (such as pads and tool sets) were explored to improve the post-polish planarity at the local interconnect level. The pad hardness was found to offer the best avenue, with up to a tenfold decrease in the post-CMP interlevel dielectric thickness range.
Starting Page	196
Ending Page	198
File Size	301652
Page Count	3
File Format	PDF
ISBN	0780342852
DOI	10.1109/IITC.1998.704790
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Geometry Dielectric materials Process control Inorganic materials Monitoring Electrical resistance measurement Research and development Laboratories Tin Etching
Content Type	Text
Resource Type	Article

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