NDLI: Comparison of two standard WLR current-ramped tests for oxide reliability

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Comparison of two standard WLR current-ramped tests for oxide reliability

Content Provider	IEEE Xplore Digital Library
Author	Lanchava, B. Baumgartner, P. Martin, A. Beyer, A. Mueller, E.
Copyright Year	2000
Description	Author affiliation: Infineon Technol. AG, Regensburg, Germany (Lanchava, B.)
Abstract	A comparison between the GOX-Reliability results obtained on 7.5 nm and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms-a CSQ (Current Step Qbd) stress on the one hand and the JEDEC J-Ramp, on the other hand-are presented. The observed influence of the ramping profile and the step holding time t/sub step/ on the reliability data shows a strong dependence on the type of device under test (DUT). The P-type MOS-devices seem to be more susceptible to the changes of the current ramping rate. The obtained results are discussed in terms of the GOX interface roughness, depletion effects during the stress, and the serial resistance of the test structure.
Starting Page	185
Ending Page	186
File Size	210212
Page Count	2
File Format	PDF
ISBN	0780363922
DOI	10.1109/IRWS.2000.911936
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Design for quality Stress Breakdown voltage Electric breakdown Electrical resistance measurement Acceleration Atomic force microscopy Voltage measurement Life estimation
Content Type	Text
Resource Type	Article

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