NDLI: System-level design of a reconfigurable CT SD modulator for multi-standard wireless applications

Content Provider	IEEE Xplore Digital Library
Author	Viera, R.A.C. Prior, C.A. de La Cruz, J. Martins, J.B.
Copyright Year	2014
Description	Author affiliation: Microelectron. Group (Gmicro), Fed. Univ. of Santa Maria (UFSM), Santa Maria, Brazil (Viera, R.A.C.; Prior, C.A.; de La Cruz, J.; Martins, J.B.)
Abstract	This paper reports the system-level design of a reconfigurable continuous-time sigma-delta modulator that is capable to perform the analog-to-digital conversion for GSM, LTE5 and WLAN wireless standards. The modulator architecture consists of a third-order loop filter using feed-forward summation topology and a 4-bit internal quantizer. The modulator coefficients were directly synthesized in the continuous-time domain which provides a more efficient modulator in terms of noise shaping, efficiently placing the zeros and poles of the noise transfer function. The reconfiguration strategy is performed at the circuit-level by using digital signals that selects the appropriate transconductances, capacitors and the sampling frequency for each standard. SIMULINK building blocks that model the non-idealities associated with the modulator were employed in the system-level simulations. The results show that the modulator achieves a signal-to-noise plus distortion ratio of 96/83/81 dB within a 0.2/5/10 MHz signal bandwidth.
Starting Page	1
Ending Page	6
File Size	2806173
Page Count	6
File Format	PDF
ISBN	9781479968732
DOI	10.1145/2660540.2660977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-01
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless LAN GSM Modulation Noise Jitter Abstracts Prototypes high order noise-shaping CT sigma-delta modulator system-level design A/D conversion
Content Type	Text
Resource Type	Article

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