NDLI: A novel system on chip for software-defined, high-speed OFDM signal processing

Content Provider	IEEE Xplore Digital Library
Author	Meyer, J. Dreschmann, M. Karnick, D. Schindler, P.C. Freude, W. Leuthold, J. Becker, J.
Copyright Year	2013
Description	Author affiliation: Inst. for Inf. Process. Technol. (ITIV), Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany (Meyer, J.; Dreschmann, M.; Becker, J.) \|\| Inst. of Photonics & Quantum Electron. (IPQ), Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany (Karnick, D.; Schindler, P.C.; Freude, W.; Leuthold, J.)
Abstract	In this paper the authors describe a novel system on chip (SoC) that is especially developed for digital signal processing of high-speed orthogonal frequency division multiplexing (OFDM) signals with data rates up to gigabits per second. Besides offering a new degree of freedom for the tradeoff between flexibility and performance during runtime, the modular concept of the SoC also allows a tradeoff between performance and costs during design time. The flexibility to adapt the OFDM system parameters by software enables even system designers without a good knowledge of hardware design to implement high-speed OFDM systems. An example configuration of the architecture was implemented on a Virtex-6 FPGA in order to set up a software-defined OFDM transmitter, achieving data rates of several gigabits per second. The paper closes with implementation and performance results of experiments using the developed transmitter and an optical transmission of the generated OFDM signals.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	6
File Size	558714
Page Count	6
File Format	PDF
ISBN	9781479911325
DOI	10.1109/SBCCI.2013.6644883
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-02
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors OFDM Random access memory Signal processing System-on-chip Field programmable gate arrays Clocks fibre SoC MPSoC FPGA high-speed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in