NDLI: A high resolution time measurement system

Content Provider	IEEE Xplore Digital Library
Author	Yamaguchi, Y. Koyanagi, N. Katano, K.
Copyright Year	1991
Description	Author affiliation: Yokogawa Electr. Corp., Tokyo, Japan (Yamaguchi, Y.; Koyanagi, N.; Katano, K.)
Abstract	A high-resolution, less than 1-ps, time measurement system (TMS) has been developed using a time-to-voltage (T/V) conversion interpolation technique. In order to accomplish the high-resolution measurement, the authors developed two specific techniques. One is the generation of an accurate interpolation pulse from the measured signal that is realized by the emitter-coupled logic (ECL)-gate-array. The other is the T/V converter which converts the pulse width to the corresponding voltage to thereby measure the pulse width. The T/V converter consists of current switches, and integrated capacitor and a buffer amplifier. The switched current charges the capacitor during the time that the interpolation pulse is on a high level. In this conversion, high-speed and accurate analog circuit design are being used, and therefore a 1-ps time resolution and a less than 10-ps linearity error are obtained. The system is composed of a wideband input amplifier, a 16-b microprocessor and a highly stabilized oscillator. The total RMS jitter using this system is less than 15-ps, and single-shot resolution is less than 1 ps. TMS has many applications, for example, time interval measurement, jitter analysis, measurement of frequency stability, etc.
Starting Page	618
Ending Page	621
File Size	236108
Page Count	4
File Format	PDF
ISBN	0879425792
DOI	10.1109/IMTC.1991.161670
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-14
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Time measurement Pulse measurements Pulse amplifiers Interpolation Pulse width modulation converters Capacitors Jitter Frequency measurement Signal resolution Pulse generation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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