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  1. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.
  2. International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
  3. Responsive Multithreaded Processor for Distributed Real-Time Processing
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2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative architecture for future generation high-performance processors and systems (iwia 2007)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems [Cover]
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems-Title
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems-Copyright
Message from the Editors
Reviewing Committee
A Holistic Approach to System Reliability in Blue Gene
Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips
Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors
The Speculative Prefetcher and Evaluator Processor for Pipelined Memory Hierarchies
Responsive Multithreaded Processor for Distributed Real-Time Processing
A Partial Irregular-Network Routing on Faulty k-ary n-cubes
Predictive Switching in 2-D Torus Routers
Hardware Support for MPI in DIMMnet-2 Network Interface
Compilation for Delay Impact Minimization in VLIW Embedded Systems
Real-Time Operating System Kernel for Multithreaded Processor
Author index
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Innovative Architecture for Future Generation High-Performance Processors and Systems
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

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Responsive Multithreaded Processor for Distributed Real-Time Processing

Content Provider IEEE Xplore Digital Library
Author Yamasaki, N.
Copyright Year 2006
Description Author affiliation: Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama (Yamasaki, N.)
Abstract Responsive multithreaded (RMT) processor is a processor chip that integrates almost all functions for parallel/distributed real-time systems such as robots, intelligent rooms/buildings, amusement systems, etc. Concretely, the RMT processor integrates a real-time processing core (RMT PU), a real-time communication (five sets of responsive links), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, etc.), and control I/O peripherals (PWM generators, pulse counters, etc.). The design rule of the RMT processor is TSMC 0.13 mum CMOS Cu 1P8M and its die size is 100 $mm^{2}.$ The RMT PU can execute eight prioritized threads simultaneously by using the SMT architecture based on priority, called the RMT architecture. Priority of real-time systems is introduced into all functional units including cache systems, a fetch unit, an issue unit, execution units, etc., so that the RMT PU can guarantee the real-time execution of the prioritized threads. If a resource conflict occurs at each functional unit, the higher priority thread can overtake the lower priority threads at the functional unit. So the RMT PU is like an SMT core with priority to execute threads simultaneously in order of priority set by a real-time operating system. The RMT PU has the hierarchical storage of thread states. The RMT PU has eight hardware contexts as the first level (native) register sets to execute the eight prioritized threads simultaneously. The RMT PU also has a context cache that can save 32 hardware contexts so as to handle and execute 40 prioritized threads concurrently by hardware
Sponsorship IEEE CPS
Starting Page 44
Ending Page 56
File Size 2463506
Page Count 13
File Format PDF
ISBN 0769526896
ISSN 15373223
DOI 10.1109/IWIAS.2006.36
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2006-01-23
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Yarn Real time systems Hardware Intelligent robots Pulse width modulation Surface-mount technology Parallel robots Intelligent structures Buildings Computer peripherals
Content Type Text
Resource Type Article
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