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  1. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.
  2. Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
  3. The bimode++ branch predictor
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2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative architecture for future generation high-performance processors and systems (iwia 2007)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Innovative architecture for future generation high-performance processors and systems
Message from the Editors
Committees
Superscalar processor with multi-bank register file
Steering and forwarding techniques for reducing memory communication on a clustered microarchitecture
The bimode++ branch predictor
On the use of bit filters in shared nothing partitioned systems
Incorporating a secure coprocessor in the database-as-a-service model
Understanding and comparing the performance of optimized JVMs
An exploration of the technology space for multi-core memory/logic chips for highly scalable parallel systems
Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in MPSoCs
A New Kind of Processor Interface for a System-on-Chip Processor with TIE Ports and TIE Queues of Xtensa LX
A multi-thread processor architecture based on the continuation model
PRESTOR-1: a processor extending multithreaded architecture
Continuum computer architecture for nano-scale and ultra-high clock rate technologies
Performance evaluation of dynamic network reconfiguration using Detour-UD routing
Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface
SIMD optimization in COINS compiler infrastructure
Performance comparison of vector-calculations between Itanium2 and other processors
Author index
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Innovative Architecture for Future Generation High-Performance Processors and Systems
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

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The bimode++ branch predictor

Content Provider IEEE Xplore Digital Library
Author Kise, K. Katagiri, T. Honda, H. Yuba, T.
Copyright Year 2005
Description Author affiliation: Graduate Sch. of Inf. Syst., Univ. of Electro-Commun., Japan (Kise, K.; Katagiri, T.; Honda, H.; Yuba, T.)
Abstract Modern wide-issue superscalar processors tend to adopt deeper pipelines in order to attain high clock rates. This trend increases the number of on-the-fly instructions in processors and a mispredicted branch can result in substantial amounts of wasted work. In order to mitigate these wasted works, an accurate branch prediction is required for the high performance processors. In order to improve the prediction accuracy, we propose the bimode++ branch predictor. It is an enhanced version of the bimode branch predictor. Throughout execution from the start to the end of a program, some branch instructions have the same result at all times. These branches are defined as extremely biased branches. The bimode++ branch predictor is unique in predicting the output of an extremely biased branch with a simple hardware structure. In addition, the bimode++ branch predictor improves the accuracy using the refined indexing and a fusion function. Our experimental results with benchmarks from SpecFP, SpecINT, multi-media and server area show that the bimode++ branch predictor can reduce the misprediction rate by 13.2% to the bimode and by 32.5% to the gshare.
File Size 521552
File Format PDF
ISBN 0769524834
ISSN 15373223
DOI 10.1109/IWIA.2005.43
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2005-01-17
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Accuracy Hardware Clocks Indexing History Information systems Pipelines Microprocessors Registers Counting circuits
Content Type Text
Resource Type Article
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