NDLI: Leakage suppression in the toric code

Content Provider	IEEE Xplore Digital Library
Author	Suchara, M. Cross, A.W. Gambetta, J.M.
Copyright Year	2015
Description	Author affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA (Suchara, M.; Cross, A.W.; Gambetta, J.M.)
Abstract	Quantum codes excel at correcting local noise but fail to correct leakage faults that excite qubits to states outside the computational space. Aliferis and Terhal have shown that an accuracy threshold exists for leakage faults using gadgets called leakage reduction units (LRUs). However, these gadgets reduce the threshold and increase experimental complexity, and the costs have not been thoroughly understood. We explore a variety of techniques for leakage resilience in topological codes. Our contributions are threefold. First, we develop a leakage model that is physically motivated and efficient to simulate. Second, we use Monte-Carlo simulations to survey several syndrome extraction circuits. Third, given the capability to perform 3-outcome measurements, we present a dramatically improved syndrome processing algorithm. Our simulations show that simple circuits with one extra CNOT per qubit reduce the accuracy threshold by less than a factor of 4 when leakage and depolarizing noise rates are comparable compared to a scenario without leakage. This becomes a factor of 2 when the decoder uses 3-outcome measurements. Finally, we make the surprising observation that for physical error rates less than 2 × $10^{-4},$ placing LRUs after every gate may achieve the lowest logical error rate. We expect that the ideas may generalize to other topological codes.
Starting Page	1119
Ending Page	1123
File Size	317667
Page Count	5
File Format	PDF
ISSN	21578117
e-ISBN	9781467377041
DOI	10.1109/ISIT.2015.7282629
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-14
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Logic gates Standards Quantum computing Fault tolerance Fault tolerant systems Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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