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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jian-Jia Weng Chih-Chieh Lai Chung-Hsuan Wang |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan 30010, R.O.C. (Jian-Jia Weng; Chih-Chieh Lai; Chung-Hsuan Wang) |
| Abstract | Previous studies on low-density parity-check convolutional codes (LDPC-CC) reveal that LDPC-CC with rational parity-check matrices (RPCM) suffer from the unaffordable decoding latency/complexity due to the infinite memory order and the poor bit-error-rate performance due to the existence of length-4 cycles in the Tanner graph. However, in this paper, we show that every LDPC-CC with RPCM can be associated with an equivalent Tanner graph which can avoid the infinite memory order and undesired short length cycles but still implements the same constraints specified by the RPCM. Together with the iterative decoding based on belief propagation with proper scheduling, simulation results indicate that LDPC-CC with RPCM can also provide satisfactory decoding performance. |
| Starting Page | 789 |
| Ending Page | 793 |
| File Size | 438962 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424478903 |
| e-ISBN | 9781424478927 |
| e-ISBN | 9781424478910 |
| DOI | 10.1109/ISIT.2010.5513631 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parity check codes Convolutional codes Iterative decoding Pipelines Delay Belief propagation Very large scale integration Polynomials Guidelines Bit error rate |
| Content Type | Text |
| Resource Type | Article |
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