NDLI: A scalable and high performance elliptic curve processor with resistance to timing attacks

Content Provider	IEEE Xplore Digital Library
Author	Hodjat, A. Hwang, D.D. Verbauwhede, I.
Copyright Year	2005
Description	Author affiliation: California Univ., Los Angeles, CA, USA (Hodjat, A.; Hwang, D.D.; Verbauwhede, I.)
Abstract	This paper presents a high performance and scalable elliptic curve processor which is designed to be resistant against timing attacks. The point multiplication algorithm (double-add-subtract) is modified so that the processor performs the same operations for every 3 bits of the scalar k independent of the bit pattern of the 3 bits. Therefore, it is not possible to extract the key pattern using a timing attack. The data flow graph of the modified algorithm is derived and the underlying Galois field operators are scheduled so that the point multiplication delay is minimized. The architecture of this processor is based on the Galois field of GF(2n) and the bit-serial field multiplier and squarer are designed. The processor is configurable for any value of n and the delay of point multiplication is [18(n+3) + (n+3)/2 + 1]/spl times/(n/3) clock cycles. For the case of GF(2/sup 163/) the point multiplication delay is 165888 clock cycles.
Starting Page	538
Ending Page	543
File Size	153634
Page Count	6
File Format	PDF
ISBN	0769523153
DOI	10.1109/ITCC.2005.32
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Elliptic curves Timing Delay Galois fields Clocks Process design Data mining Flow graphs Scheduling algorithm Processor scheduling
Content Type	Text
Resource Type	Article

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