NDLI: A RDT-based interconnection network for scalable network-on-chip designs

Content Provider	IEEE Xplore Digital Library
Author	Yang Yu Mei Yang Yulu Yang Yingtao Jiang
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci., Nankai Univ., Tianjin, China (Yang Yu)
Abstract	The interconnection network plays an important role in the performance and energy consumption of a network-on-chip (NoC) system. In this paper, we propose a RDT(2,2,1)//spl alpha/-based interconnection network for NoC designs. RDT(2,2,1)//spl alpha/ is constructed by recursively overlaying 2D diagonal meshes (torus). The number of layers needed for routing the links in RDT(2,2,1)//spl alpha/ is shown to be bounded at 6, which is feasible to be implemented with current and future VLSI technologies. With the innovative diagonal structure and its simple rank assignment, RDT(2,2,1)//spl alpha/ possesses the following features: recursive structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8, and robust routing schemes. These features make RDT(2,2,1)//spl alpha/ a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy-efficiency, customizability, and fault-tolerance.
Starting Page	723
Ending Page	728
File Size	673964
Page Count	6
File Format	PDF
ISBN	0769523153
DOI	10.1109/ITCC.2005.30
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiprocessor interconnection networks Network-on-a-chip Routing Energy consumption Very large scale integration Network topology Robustness Scalability Energy efficiency Fault tolerance routing Network-on-Chip interconnection network torus scalability
Content Type	Text
Resource Type	Article

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