NDLI: Affinity-aware HPC applications in multichip and multicore multiprocessor

Content Provider	IEEE Xplore Digital Library
Author	Velkoski, G. Ristov, S. Gusev, M.
Copyright Year	2013
Description	Author affiliation: Fac. of Inf. Sci. & Comput. Eng., Ss. Cyril & Methodius Univ., Skopje, Macedonia (Velkoski, G.; Ristov, S.; Gusev, M.)
Abstract	Introducing multi level cache memory reduces the gap between the CPU and main memory and speeds up the program execution. The speedup in modern multiprocessors can scale up to linear speedup according to Gustafson's law. Each CPU core usually possesses private L1 and L2 cache memory and shares L3 cache memory in multi-core processor architectures. Furthermore, private or shared cache memory could have significant impact to the algorithm performance in parallel implementation. Private cache increases the overall cache size used during the execution. On the other hand, shared cache reduces cache misses if all CPU cores use the same data. In this paper we analyze the matrix vector multiplication algorithm performance for sequential and parallel implementation in multi-chip multi-core multiprocessor in order to determine the CPU affinity that provides the best performance. We also realize theoretical analysis to determine the problem size regions where selecting appropriate CPU affinity can produce the best performance using the same resources.
Starting Page	95
Ending Page	100
File Size	661947
Page Count	6
File Format	PDF
ISBN	9789537138301
ISSN	13342762
e-ISBN	9789537138325
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-24
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	SRCE University Computing Centre, University of Zagreb
Subject Keyword	Speed CPU Cache Matrix - Vector Multiplication Performance
Content Type	Text
Resource Type	Article

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