NDLI: An efficient technique for processor automatic functional test generation based on evolutionary strategies

Content Provider	IEEE Xplore Digital Library
Author	Hudec, J.
Copyright Year	2011
Description	Author affiliation: Slovak University of Technology, Institute of Computer Systems and Networks, Faculty of Informatics and Information Technologies, Ilkovičova 3, 842 16 Bratislava, Slovak Republic (Hudec, J.)
Abstract	This paper presents some results in the design and implementation of a universal functional test generator for VLSI circuits, such as microprocessor and processor cores. Our approach to test generation - the functional test generation method - is based on knowledges of instruction set architecture (ISA), functional description of VLSI systems at functional VHDL level and promising concept of software-based self test (SBST); for better test generation the genetic algorithm (GA) properties based on evolutionary strategies are used. The algorithm for automatic generation of functional test of processors (normal executable test sequence of instructions) is used in very flexible and effective tool - Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction testing mixes is also discussed.
Starting Page	527
Ending Page	532
File Size	360210
Page Count	6
File Format	PDF
ISBN	9781612848976
ISSN	13301012
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-27
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	University of Zagreb
Subject Keyword	Testing Genetic algorithms Generators Microprocessors Very large scale integration Circuit faults Assembly test simulation and verification VLSI functional testing processor functional test generation SBST
Content Type	Text
Resource Type	Article

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