NDLI: Buffer allocation for frame reassembly and queueing in ATM networks

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Buffer allocation for frame reassembly and queueing in ATM networks

Content Provider	IEEE Xplore Digital Library
Author	Humblet, P.A. Lee, W.C. Hluchyj, M.G.
Copyright Year	1994
Description	Author affiliation: MIT, Cambridge, MA, USA (Humblet, P.A.)
Abstract	Buffer allocation for frame reassembly and queueing in the destination node of an ATM subnetwork supporting multiple frame relay connections is examined. The finite peak rate of a frame relay connection is explicitly modeled and shown to be an important factor in buffer sizing. Specifically, the average number of buffers required is shown to be large when many low-peak-rate frame relay connections are multiplexed for delivery to a single high-speed frame relay interface port, but the tail of the distribution is determined only by aggregate traffic statistics.
Starting Page	510
Ending Page	515
File Size	469981
Page Count	6
File Format	PDF
ISBN	0818655704
DOI	10.1109/INFCOM.1994.337692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-06-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Intelligent networks Frame relay Asynchronous transfer mode Queueing analysis Random variables Probability distribution Aggregates Statistical distributions Feeds Traffic control
Content Type	Text
Resource Type	Article

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