NDLI: Reliability and performance of multi-level loop computer networks

Content Provider	IEEE Xplore Digital Library
Author	Heidtmann, K.D.
Copyright Year	1992
Description	Author affiliation: Dept. of Comput. Sci., Hamburg Univ., Germany (Heidtmann, K.D.)
Abstract	An improved network architecture which incorporates high reliability, high performance, and optimal accommodation to environmental topologies is presented. The network investigated is tree-shaped, where the leaves represent host computers or loop subnetworks and the vertices are ring adapters attaching hosts or bridges interconnecting subnetworks. For ease of modeling only balanced and homogeneous structures are considered where loop subnetworks have the same topology. Multilevel hierarchical loop networks have minimal diameter when the number of nodes in the subnetworks is proportional to the root of the number of all attached stations. In this case, the diameter grows only with the logarithm of the number of stations. This implies that network reliability and performance are significantly improved using the proposed multilevel hierarchical architecture. The performance analysis assumes the protocol of buffer insertion.
Starting Page	1089
Ending Page	1095
File Size	667978
Page Count	7
File Format	PDF
ISBN	0780306023
DOI	10.1109/INFCOM.1992.263468
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer network reliability Network topology Fault tolerance Computer networks Floors Joining processes Computer architecture Urban areas Buildings Computer science
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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