NDLI: A petabit photonic packet switch (P/sup 3/S)

Content Provider	IEEE Xplore Digital Library
Author	Chao, H.J. Deng, K.-L. Jing, Z.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Polytech. Univ., Brooklyn, NY, USA (Chao, H.J.)
Abstract	This paper presents a new petabit photonic packet switch (P/sup 3/S) architecture that is highly scalable both in dimension and capacity while maintaining high system performances. Using a new multidimensional photonic multiplexing scheme that includes space, time, wavelength, and subcarrier domains, we propose a photonic switch fabric based on a 3-stage Clos network to provide scalable large-dimension photonic interconnections with nanosecond reconfiguration speed. Packet buffering is implemented electronically at the input and output port controllers, allowing the central photonic switch fabric to transport high-speed optical signals without electrical-to-optical conversion. Optical time division multiplexing (OTDM) technology further scales port speed beyond electronic speed up to 160 Gbits/s to minimize the fiber connections. To solve output contention, we propose a new arbitration scheme, called frame-based exhaustive matching (FEM), using extended frames to aggregate cells from different incoming lines. The extended frame relaxes the stringent arbitration time constraint at a 160 Gbit/s port speed. Based on the FEM scheme in the proposed architecture, a 6400 /spl times/ 6400 switch with a total capacity of 1.024 petabit/s can be achieved with throughput close to 100% under various traffic conditions.
Sponsorship	IEEE Comput. Soc. IEEE Commun. Soc. Nat. Sci. Foundation
Starting Page	775
Ending Page	785
File Size	696030
Page Count	11
File Format	PDF
ISBN	0780377524
ISSN	0743166X
DOI	10.1109/INFCOM.2003.1208727
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packet switching Optical buffering Optical packet switching Optical switches Fabrics High speed optical techniques Optical interconnections Multidimensional systems WDM networks Centralized control
Content Type	Text
Resource Type	Article
Subject	Computer Science Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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