NDLI: The rate mismatch problem in heterogeneous ABR flow control

Content Provider	IEEE Xplore Digital Library
Author	Plotkin, N.T. Sydir, J.J.
Copyright Year	1997
Description	Author affiliation: SRI Int., Menlo Park, CA, USA (Plotkin, N.T.)
Abstract	Because the ATM Forum does not standardize the ABR flow control algorithm that an ATM switch should run, some ATM networks are likely to contain switches that run different ABR flow control algorithms. Even if all the switches within a "cloud" of switches use the same algorithm, individual clouds (each with it own algorithm) will be interconnected by virtual circuits. Virtual circuits which traverse multiple clouds will therefore be controlled by two different flow control algorithms concurrently. We explore some of the ramifications of mixing different flow control algorithms in the same ATM network. We identify the rate mismatch problem, which arises when a nonbottleneck switch (that uses one algorithm) interferes with the control of the bottleneck switch (that uses another algorithm). We formulate a hypothesis that states the conditions that lead to the rate mismatch problem. These conditions identify a specific class of problematic topologies. We validate the hypothesis formally and prove that rate mismatch causes unfairness. Using four different algorithms, in combinations of two at a time, we illustrate the interoperability of ABR flow control algorithms.
Starting Page	1304
Ending Page	1314
File Size	1068236
Page Count	11
File Format	PDF
ISBN	0818677805
ISSN	0743166X
DOI	10.1109/INFCOM.1997.631163
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-04-07
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Asynchronous transfer mode Clouds Network topology Circuit topology Switching circuits Virtual colonoscopy Intelligent networks Integrated circuit interconnections Bit rate
Content Type	Text
Resource Type	Article
Subject	Computer Science Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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