NDLI: High-level synthesis of multithreaded processor based image generator

Content Provider	IEEE Xplore Digital Library
Author	Onoye, T. Masaki, T. Asahara, S. Sagishima, T. Shirakawa, I. Tsukiyama, S. Shinoda, S.
Copyright Year	1994
Description	Author affiliation: Dept. of Inf. & Syst. Eng., Osaka Univ., Japan (Onoye, T.; Masaki, T.)
Abstract	Design of a multithreaded processor dedicated to image generation is described, which can be achieved mainly by means of a high-level synthesis tool PARTHENON. The processor employs a multithread architecture which is a novel and promising approach to parallel image generation. This paper describes a high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to prove a practicability of the designed processor. The processor improves the throughput for image generation by the factor of 2.4 times, compared with the conventional design method.
Starting Page	47
Ending Page	52
File Size	542190
Page Count	6
File Format	PDF
ISBN	0780319613
DOI	10.1109/ISIE.1994.333130
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-25
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Image generation Parallel processing Hardware Streaming media Process design Throughput HDTV Information systems Industrial electronics
Content Type	Text
Resource Type	Article

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