NDLI: Bipolar transistors under positive and negative gate bias stress

Content Provider	IEEE Xplore Digital Library
Author	Maiga, C.O. Tala-Ighil, B. Toutah, H. Boudart, B.
Copyright Year	2005
Description	Author affiliation: Ecole d'Ingenieurs de Cherbourg, Laboratoire Univ. des Sci. Appliquees de Cherbourg, France (Maiga, C.O.; Tala-Ighil, B.; Toutah, H.; Boudart, B.)
Abstract	The work presented in this paper is concerned with the effects of a positive and of a negative gate bias stress on punch-through insulated gate bipolar transistors (PT-IGBT's). Two selections of PT IGBT's all of the same nominal range were gate biased at their positive and negative maximum gate-to-emitter voltage with drain and emitter short-circuited at 140 /spl deg/C during 1200 hours. A particular interest was taken in the switching parameters. Experimental results on their evolution under the two types of stress are presented in a quantified way. Then, a qualitative analysis of the effects of the switching times shift, due to the IGBT's ageing, on a PWM inverter operation is presented.
Starting Page	435
Ending Page	440
File Size	214507
Page Count	6
File Format	PDF
ISBN	0780387384
DOI	10.1109/ISIE.2005.1528956
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-20
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Insulated gate bipolar transistors Stress Aging Voltage Pulse width modulation inverters Static power converters Manufacturing MOSFET circuits Substrates Bipolar transistors
Content Type	Text
Resource Type	Article

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