NDLI: MORRPH: a modular and reprogrammable real-time processing hardware

Content Provider	IEEE Xplore Digital Library
Author	Drayer, T.H. Tront, J.G. King IV, W.E. Conners, R.W.
Copyright Year	1990
Description	Author affiliation: Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA (Drayer, T.H.; Tront, J.G.; King, W.E., IV; Conners, R.W.)
Abstract	MORRPH is a general-purpose reconfigurable processing unit, primarily intended for real-time 2-dimensional image processing. Its flexible architecture allows it to be used for other applications including 1-dimensional signal processing, 2-dimensional cellular automata problems, and 3-dimensional image processing. The modular, open-ended (incompletely specified) architecture consists of a rectangular mesh of processing elements. Each processing element contains one socket for a field programmable gate array (FPGA) chip and one socket for support processing chips. The FPGA chips provide an array of logic resources, consisting of combinational logic functions, flip-flops, and interconnections. Empty support sockets allow several discrete IC chips to be tightly coupled to each FPGA, the type of IC is determined by the individual requirements of the task to be performed by the MORRPH board. This allows the support chips to implement functions that are not efficiently realized by the FPGAs. These memory, arithmetic, or processing support chips are specified when a particular application is compiled for the MORRPH board. If a single MORRPH board does not provide enough computational power for a particular application, several MORRPH boards can be interconnected to solve the task. The MORRPH architecture is implemented as an adapter The modular nature of the MORRPH architecture at both the chip and board level allows a very efficient implementation of a required machine vision task.
Starting Page	211
Ending Page	215
File Size	467576
Page Count	5
File Format	PDF
ISBN	0780373693
DOI	10.1109/ISIE.1995.496628
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-07-10
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Field programmable gate arrays Sockets Image processing Programmable logic arrays Logic arrays Computer architecture Array signal processing Logic functions Flip-flops
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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