NDLI: Proposal for a field-evolvable hardware based on a microprocessor incorporated flash memory

Content Provider	IEEE Xplore Digital Library
Author	Sato, Y.
Copyright Year	2001
Description	Author affiliation: Dept. of Comput. Sci., Hosei Univ., Tokyo, Japan (Sato, Y.)
Abstract	A new idea for evolvable hardware based on a microprocessor is proposed. Evolvable hardware is a new direction in hardware research that fuses evolutionary computation and reconfigurable logic LSI circuits. In recent years, there has been much research using programmable logic devices (PLDs) and field programmable gate arrays (FPGAs). In particular, the application of digital circuit evolution to engineering fields has already begun. On the other hand, the long learning time, the difficulty of predicting when an effective capability will appear, the large chip size and other such problems have hindered progress in diffusion into engineering fields. We propose RTL (register transfer level) evolution performed on a microprocessor as a means of addressing these problems, Specifically, we propose: (1) incorporating flash memory into the microprocessor to allow on-board programming and reprogramming, (2) using genetic algorithms to provide an RTL learning capability, and (3) the use of a framework that provides for the coexistence of static programs and programs that self-organize through learning. On the basis of a simple hand-design, we concluded that the proposed method is more effective in terms of learning efficiency and reliability than the conventional approach using FPGAs and PLDs.
Starting Page	608
Ending Page	615
File Size	623592
Page Count	8
File Format	PDF
ISBN	0780366573
DOI	10.1109/CEC.2001.934447
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-27
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Proposals Hardware Microprocessors Field programmable gate arrays Programmable logic arrays Fuses Evolutionary computation Reconfigurable logic Large scale integration Circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA implementation of a reconfigurable microprocessor

Intrinsic evolution of digital circuits based on a reconfigurable hyper-structure

An efficient configuration unit design for VLIW based reconfigurable processors

A reconfigurable signal processing IC with embedded FPGA and multiport Flash memory

A combinatorial digital circuit with evolutionary algorithm for evolvable hardware software codesign

Evolvable hardware with development

VHDL design automation using evolutionary computation

A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

The Nano Processor: a low resource reconfigurable processor

Proposal for a field-evolvable hardware based on a microprocessor incorporated flash memory

Similar Documents

FPGA implementation of a reconfigurable microprocessor

Intrinsic evolution of digital circuits based on a reconfigurable hyper-structure

An efficient configuration unit design for VLIW based reconfigurable processors

A reconfigurable signal processing IC with embedded FPGA and multiport Flash memory

A combinatorial digital circuit with evolutionary algorithm for evolvable hardware software codesign

Evolvable hardware with development

VHDL design automation using evolutionary computation

A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

The Nano Processor: a low resource reconfigurable processor

Proposal for a field-evolvable hardware based on a microprocessor incorporated flash memory