NDLI: A three-valued fast fault simulator for scan-based VLSI-logic

Content Provider	IEEE Xplore Digital Library
Author	Schulz, M.H. Pellkofer, D.
Copyright Year	1989
Description	Author affiliation: Dept. of Electr. Eng., Tech. Univ., Munich, West Germany (Schulz, M.H.; Pellkofer, D.)
Abstract	Based on an effective three-valued coding, the methods of two-valued fault simulation are extended to three-valued fault simulation. Solidly and potentially detected faults are considered. Parallel processing of patterns is applied at all stages of the calculation procedure, and the expensive fault simulation is restricted to fanout stems by adopting the concept of fanout-free regions. In addition, the exploitation of the dominance relationships between signals of a combinational circuit is shown to lead not only to an acceleration of the fault-simulation process, but also to improvements in fault-detection accuracy. Experimental benchmark results substantiate the efficiency of the approach and demonstrate that three-valued fault simulation can be almost as fast as two-valued fault simulation.<>
Starting Page	41
Ending Page	48
File Size	672231
Page Count	8
File Format	PDF
ISBN	0818619376
DOI	10.1109/ETC.1989.36218
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-04-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Electrical fault detection Circuit testing Fault detection Computational modeling Combinational circuits Computer simulation Parallel processing Logic circuits
Content Type	Text
Resource Type	Article

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