NDLI: An ASIC RISC-based I/O processor for computer applications

Content Provider	IEEE Xplore Digital Library
Author	Cates, R.L. Farrell III, J.J.
Copyright Year	1990
Description	Author affiliation: VLSI Technol. Inc., Tempe, AZ, USA (Cates, R.L.; Farrell, J.J., III)
Abstract	Describes a hard disk controller application and the RISC-based ISA Bus coprocessor called the I/O processor (IOP) from which the hard disk application was developed. The IOP is used as a central element in ISA (Industry Standard Architecture)-based peripheral controller applications. In this specific application, it incorporates a comprehensive set of function blocks in addition to the core 32-bit RISC processor. These include an ISA address decoder, a register file compatible with the PC/AT-compatible hard disk controller, a DRAM controller capable of support 16 M bytes of 32-bit memory, an interrupt controller, a DMA controller, a 2 K-byte ROM and a 512-byte RAM. The IOP has been optimized for application requiring high data transfer rates. Burst data transfers up to 40 M bytes per second may be attained with the RISC processor running at 10 MHz. A paging and interleaving DRAM controller is utilized so that slower DRAMs with 100 nanoseconds access times can be used.<>
Starting Page	50
Ending Page	55
File Size	578823
Page Count	6
File Format	PDF
ISBN	0818620668
DOI	10.1109/EASIC.1990.207909
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-05-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Computer applications Application software Hard disks Instruction sets Random access memory Reduced instruction set computing Coprocessors Industrial control Centralized control
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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