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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ligon III, W.B. Ramachandran, U. |
| Copyright Year | 1990 |
| Description | Author affiliation: Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA (Ligon, W.B., III; Ramachandran, U.) |
| Abstract | An approach to designing computer architectures in which architectural features are analyzed for utility and cost with respect to the system software that uses them is applied to reconfigurable architectures. A notation for classifying reconfigurable architectures that covers three major areas of reconfigurable architecture design-processor reconfiguration, control reconfiguration, and connection reconfiguration-is presented. A simulator based on this notation, called the reconfigurable architecture workbench, is described. This has been used to study the effects of processor reconfiguration within the image-processing application domain. Experimental results showing that some types of processor reconfiguration provide significant speedup over parallel architectures without processor reconfiguration are presented. The engineering problems present in implementing processor reconfiguration are explored, and some solutions to these problems are suggested.< |
| Starting Page | 205 |
| Ending Page | 214 |
| File Size | 777381 |
| Page Count | 10 |
| File Format | |
| ISBN | 0818620536 |
| DOI | 10.1109/FMPC.1990.89461 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-10-08 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reconfigurable architectures Computer architecture Parallel processing Process control Parallel architectures Application software Computer aided instruction Costs Computational modeling Analytical models |
| Content Type | Text |
| Resource Type | Article |
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