NDLI: A system for evaluating performance and cost of SIMD array designs

Content Provider	IEEE Xplore Digital Library
Author	Herbordt, M.C. Cravy, J. Sam, R. Kidwai, O. Lin, C.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Houston Univ., TX, USA (Herbordt, M.C.)
Abstract	SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem this work addresses is the evaluation of SIMD arrays with respect to complex applications while accounting for operating frequency and chip area. The method we use is to bridge the gap between architecture-level and EDA-level modeling by using an EDA-based tool to calibrate architectural simulations. The resulting system retains much of the high throughput of the architecture-level simulator but also has accuracy similar to that of an early pass EDA synthesis and circuit simulation. We have used our system to evaluate hundreds of potential SIMD array designs with respect to real applications. Some of the results were surprising: the slowdown caused by underutilized resources was significantly more than we had anticipated.
Starting Page	16
Ending Page	24
File Size	318054
Page Count	9
File Format	PDF
ISBN	0769500870
DOI	10.1109/FMPC.1999.750580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-02-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Application software Electronic design automation and methodology Circuit simulation Coprocessors Read-write memory Frequency Throughput Concurrent computing Space technology
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in