NDLI: A new small-dimensions full PLL system

Content Provider	IEEE Xplore Digital Library
Author	Vorokhovsky, Y.L. Gidon, G.D. Dobrovolsky, A.A.
Copyright Year	2005
Description	Author affiliation: Morion Inc., St. Petersburg, Russia (Vorokhovsky, Y.L.; Gidon, G.D.; Dobrovolsky, A.A.)
Abstract	During last years super low-noise high-frequency oscillators have got more and more applications in a number of new systems. This kind of HF OCXO usually has low temperature and long-term stability. Higher stability may be achieved in a phase locked loop system (PLL) using a low-frequency precision oscillator as a reference. Such a system usually has big size and high power consumption. One of the ways to solve this problem is to use a combined oven for both of OCXO. But then some problems because of different temperature level and stability required for both OCXO have appeared. One more problem is to save the low noise floor of HF OCXO in close presence of another OCXO. During the last year the design of such a small size full PLL system including both OCXO was made using a special calculation to minimize temperature gradients in a reference crystal in the presence of high-frequency crystal. The optimized topology in a planar-designed system allows the saving of the noise floor of HF OCXO. The achieved main parameters of the PLL-OCXO model described above are: frequency 100 MHz; noise floor -165...-170 dBc; frequency stability versus temperature range -40...+70/spl deg/C /spl plusmn/5/spl middot/10/sup -10/; long-term stability /spl plusmn/5/spl middot/10/sup -8//year; power consumption (steady state) <2.5 W; dimensions 50.8/spl middot/50.8/spl middot/16 mm.
Starting Page	426
Ending Page	428
File Size	1218026
Page Count	3
File Format	PDF
ISBN	0780384148
ISSN	10756787
DOI	10.1109/FREQ.2004.1418494
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Stability Hafnium Temperature Oscillators Energy consumption Frequency Ovens Topology Power system modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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