NDLI: VLSI architectures for field programmable gate arrays: a case study

Content Provider	IEEE Xplore Digital Library
Author	Woods, R. Cassidy, A. Gray, J.
Copyright Year	1996
Description	Author affiliation: Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK (Woods, R.)
Abstract	The ability to achieve highly efficient hardware implementations of algorithms will form a key aspect in the success of custom computing, Developments in VLSI architectures where regularity, simple design and locality of connections appears to be an ideal approach in the development of efficient field programmable gate array (FPGA) designs. The authors present a case study namely the implementation of the majority of a two dimensional (2D) discrete cosine transform (DCT) in a XilinK XC6216 device. The design has a 70% hardware utilisation figure and operates at 25 Mega pixels per second or over 30 frames per second for standard NTSC. The paper clearly demonstrates the hardware efficiency of such an approach. The paper also describes work on architectural synthesis framework to automatically generate highly regular designs for a wider range of complex algorithms.
Starting Page	2
Ending Page	9
File Size	656264
Page Count	8
File Format	PDF
ISBN	0818675489
DOI	10.1109/FPGA.1996.564736
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-04-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very-large-scale integration
Content Type	Text
Resource Type	Article

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VLSI architectures for field programmable gate arrays: a case study