NDLI: Universal emulations with sublogarithmic slowdown

Content Provider	IEEE Xplore Digital Library
Author	Kaklamanis, C. Krizanc, D. Rao, S.
Copyright Year	1993
Description	Author affiliation: DIMACS Center, Rutgers Univ., Piscataway, NJ, USA (Kaklamanis, C.)
Abstract	The existence of bounded degree networks which can emulate the computation of any bounded degree network of the same size with logarithmic slowdown is well-known. The butterfly is an example of such a universal network. Leiserson was the first to introduce the concept of an area-universal network: a network with VLSI layout area A which can emulate any network of the same size and layout area with logarithmic slowdown. His results imply the existence of an N-node network with layout area O(N log/sup 2/ N) which can emulate any N-node planar network with O(log N) slowdown. The main results of this paper are: There exists an N-node network with layout area O(N log/sup 2/ N) which can emulate any N-node planar network with O(loglogN) slowdown. The N-node butterfly (and hypercube) can emulate any network with VLSI layout area N/sup 2-/spl epsiv// (/spl epsiv/>0) with O(loglogN) slowdown. We also discuss sublogarithmic bounds for the slowdown of emulations of arbitrary bounded degree networks.<>
Starting Page	341
Ending Page	350
File Size	877020
Page Count	10
File Format	PDF
ISBN	0818643706
DOI	10.1109/SFCS.1993.366853
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Emulation Computer networks Grid computing National electric code Very large scale integration Multiprocessor interconnection networks Computational modeling Computer science Hypercubes Design engineering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

SIMD-emulations of hypercubes and related networks

Computational Properties of Mesh Connected Trees: Versatile Architectures for Parallel Computation

Hierarchical 3D-torus interconnection network

The hyper-deBruijn multiprocessor networks

A hierarchical fault-tolerant interconnection network

On the hierarchical hypercube interconnection network

Parallel Numerical Interpolation on Necklace Hypercubes

A new design methodology for optical hypercube interconnection network

Bisection widths of transposition graphs

Universal emulations with sublogarithmic slowdown

Similar Documents

SIMD-emulations of hypercubes and related networks

Computational Properties of Mesh Connected Trees: Versatile Architectures for Parallel Computation

Hierarchical 3D-torus interconnection network

The hyper-deBruijn multiprocessor networks

A hierarchical fault-tolerant interconnection network

On the hierarchical hypercube interconnection network

Parallel Numerical Interpolation on Necklace Hypercubes

A new design methodology for optical hypercube interconnection network

Bisection widths of transposition graphs

Universal emulations with sublogarithmic slowdown