NDLI: All pairs almost shortest paths

Content Provider	IEEE Xplore Digital Library
Author	Dor, D. Halperin, S. Zwick, U.
Copyright Year	1996
Description	Author affiliation: Dept. of Comput. Sci., Tel Aviv Univ., Israel (Dor, D.)
Abstract	Let G=(V,E) be an unweighted undirected graph on n vertices. A simple argument shows that computing all distances in G with an additive one-sided error of at most 1 is as hard as Boolean matrix multiplication. Building on recent work of D. Aingworth et al. (1996), we describe an O/spl tilde/(min{n/sup 3/2/m/sup 1/2/,n/sup 7/3/}) time algorithm APASP/sub 2/ for computing all distances in G with an additive one-sided error of at most 2. The algorithm APASP/sub 2/ is simple, easy to implement, and faster than the fastest known matrix multiplication algorithm. Furthermore, for every even k>2, we describe an O/spl tilde/(min{n/sup 2-(2)/(k+2)/m/sup (2)/(k+2)/, n/sup 2+(2)/(3k-2)/}) time algorithm APASP/sub k/ for computing all distances in G with an additive one-sided error of at most k. We also give an O/spl tilde/(n/sup 2/) time algorithm APASP/sub /spl infin// for producing stretch 3 estimated distances in an unweighted and undirected graph on n vertices. No constant stretch factor was previously achieved in O/spl tilde/(n/sup 2/) time. We say that a weighted graph F=(V,E') k-emulates an unweighted graph G=(V,E) if for every u, v/spl isin/V we have /spl delta//sub G/(u,v)/spl les//spl delta//sub F/(u,v)/spl les//spl delta//sub G/(u,v)+k. We show that every unweighted graph on n vertices has a 2-emulator with O/spl tilde/(n/sup 3/2/) edges and a 4-emulator with O/spl tilde/(n/sup 4/3/) edges. These results are asymptotically tight. Finally, we show that any weighted undirected graph on n vertices has a 3-spanner with O/spl tilde/(n/sup 3/2/) edges and that such a 3-spanner can be built in O/spl tilde/(mn/sup 1/2/) time. We also describe an O/spl tilde/(n(m/sup 2/3/+n)) time algorithm for estimating all distances in a weighted undirected graph on n vertices with a stretch factor of at most 3.
Starting Page	452
Ending Page	461
File Size	1002080
Page Count	10
File Format	PDF
ISBN	0818675942
ISSN	02725428
DOI	10.1109/SFCS.1996.548504
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer science Computer errors Upper bound
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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