NDLI: Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy

Content Provider	IEEE Xplore Digital Library
Author	Junyi Xie Xinyu Niu Lau, A.K.S. Tsia, K.K. So, H.K.H.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput., Sch. of Eng., Imperial Coll. London, London, UK (Xinyu Niu) \|\| Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, Hong Kong, China (Junyi Xie; Lau, A.K.S.; Tsia, K.K.; So, H.K.H.)
Abstract	With the fundamental trade-off between speed and sensitivity, existing quantitative phase imaging (QPI) systems for diagnostics and cell classification are often limited to batch processing only small amount of offline data. While quantitative asymmetric-detection time-stretch optical microscopy (Q-ATOM) offers a unique optical platform for ultrafast and high-sensitivity quantitative phase cellular imaging, performing the computationally demanding backend QPI phase retrieval and image classification in real-time remains a major technical challenge. In this paper, we propose an optimized architecture for QPI on FPGA and compare its performance against CPU and GPU implementations in terms of speed and power efficiency. Results show that our implementation on single FPGA card demonstrates a speedup of 9.4 times over an optimized C implementation running on a 6-core CPU, and 3.47 times over the GPU implementation. It is also 24.19 and 4.88 times more power-efficient than the CPU and GPU implementation respectively. Throughput increase linearly when four FPGA cards are used to further improve the performance. We also demonstrate an increased classification accuracy when phase images instead of single-angle ATOM images are used. Overall, one FPGA card is able to process and categorize 2497 cellular images per second, making it suitable for real-time single-cell analysis applications.
Starting Page	1
Ending Page	8
File Size	1939213
Page Count	8
File Format	PDF
e-ISBN	9781467390910
DOI	10.1109/FPT.2015.7393123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	New Zealand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Kernel Computer architecture Microprocessors Support vector machines Imaging Graphics processing units power efficiency quantitative phase imaging cell classification time-stretch imaging image-based single-cell analysis real-time ultra-fast events FPGA GPU acceleration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Matched Filter Computation on FPGA, Cell and GPU

Modular & scalable ultrasound platform with GPU processing

Molecular Docking on FPGA and GPU Platforms

FPGA-GPU architecture for kernel SVM pedestrian detection

Enumeration of Costas Arrays Using GPUs and FPGAs

SVM with OpenCL: High performance implementation of support vector machines on heterogeneous systems

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Hardware acceleration of SVM-based traffic classification on FPGA

Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing

Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy

Similar Documents

Matched Filter Computation on FPGA, Cell and GPU

Modular & scalable ultrasound platform with GPU processing

Molecular Docking on FPGA and GPU Platforms

FPGA-GPU architecture for kernel SVM pedestrian detection

Enumeration of Costas Arrays Using GPUs and FPGAs

SVM with OpenCL: High performance implementation of support vector machines on heterogeneous systems

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Hardware acceleration of SVM-based traffic classification on FPGA

Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing

Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy